Trace-based Out-of-Order CPU Simulator
A lightweight, cycle-accurate 4-way-wide out-of-order CPU simulator in C++.
Advisor: Prof. Moinuddin K. Qureshi, Georgia Tech · Aug 2024 – Dec 2024
A lightweight, cycle-accurate, 4-way-wide out-of-order CPU simulator built in C++.
- Modeled a multi-level cache hierarchy and replacement policies (LRU, LFU, and more).
- Implemented static (way-partitioning) and dynamic (utility-based) cache partitioning schemes.