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PhD in Computer Science

• GPA - 4.0/4.0

Bachelor of Technology, Electrical Engineering (with Honors)

• GPA - 9.1/10

Accelerating Diffusion Model Inference on NVIDIA GPUs

• Working on HiDeS, an algorithm-system co-design approach using hierarchical sparsity to accelerate block-diffusion model inference via selective recomputation across three granularities - layer, token, and column.
• Built custom CUDA kernels for attention and MLP to support selective recomputation.
• Built on top of the Fast-dLLM v2 block-diffusion model, achieving 2.33x and 2.67x speedups on A100 and H100 GPUs respectively.

Modeling DNN Operators for ASTRA-sim using Machine Learning

• Worked to accelerate ASTRA-sim, an open-source infrastructure that models the full hardware-software co-design stack of distributed ML training systems.
• Profiled operators such as GEMM and Collectives for state-of-the-art LLMs on NVIDIA GPUs using CUDA.
• Developed ML models to replace Scale-Sim, a systolic-array simulator, to estimate execution timings of arbitrary GEMM operators.

Security Assessment of ARM Desktop CPUs

• Worked toward mounting side-channel attacks by reverse-engineering ARM-based Snapdragon desktop CPUs.
• Reverse-engineered microarchitectural components such as prefetchers and the RSB using custom kernel modules on Snapdragon X Elite processors to mount attacks like RSB-based Spectre.

Avatar Cache - On-Demand Security with a Morphable Cache Architecture

• Proposed a morphable cache design that provides security on demand at state-of-the-art cache design complexity.
• On-demand security lets users opt out of security to avoid performance and power overheads.
• Implemented on the ChampSim multi-core simulator, demonstrating 0.2% performance overhead, 2% power overhead, and 0.9% storage overhead in secure mode.

Storage-efficient and Secure Fully-associative Last-level Cache

• Proposed a secure, storage-efficient shared LLC to mitigate eviction-based side-channel attacks.
• Decoupled tag and data store with pointer-based indirection for 0% storage overhead over the non-secure baseline LLC with minimal performance impact.
• Reduced data store size by 50% while maintaining Mirage-level security without hurting performance.

Research Associate - PhD

• Implemented execution of GPU kernels on concurrent streams with inter-kernel data dependency to analyze performance gains from relaxing global synchronization constraints.
• Leveraged memory access patterns and inter-kernel thread-block dependencies for Llama-3.1 in vLLM with a complete Triton backend to identify concurrent-execution dispatch opportunities.
• Developed fine-grained dispatch strategies using global semaphores to overlap data-dependent kernel execution while preserving correctness, targeting higher throughput and lower dispatch overhead.

Digital Systems Intern

• Analyzed interrupt signals of a RADAR SOC built for automotive applications.
• Developed Verilog logic to classify pulse-triggered vs level-triggered interrupt behaviour.
• Designed a SystemVerilog Assertion flow to detect anomalies early in design and testing, and automated status monitoring of all interrupt signals with Python and SystemVerilog.

Embedded Systems Intern

• Developed a solar-powered wireless data acquisition system using two ESP32-WROOM modules.
• Designed a Li-ion charging circuit with dynamic power-path management and solar panels for uninterrupted power to a remote ESP32 node.
• Built a Python GUI to collect data from the remote node and maintain a PostgreSQL database.

Trace-based Out-of-Order CPU Simulator

• Designed a lightweight, cycle-accurate, 4-way-wide out-of-order CPU simulator in C++.
• Modeled a multi-level cache hierarchy and replacement policies (LRU, LFU, etc.).
• Implemented static (way-partitioning) and dynamic (utility-based) cache partitioning schemes.

Out-of-Order Superscalar Processor

• Led a four-member team to design a 2-wide superscalar out-of-order processor.
• Designed a 2-bit branch predictor, Fetch, Decode, Reservation Station, and ROB with register renaming.
• Implemented and tested the full design in VHDL on Quartus Prime.

Hazardous Gas Detection using Nanosaur with VSLAM

• Designed an add-on circuit to detect NH3, CO2, CO, CH4 and other gases for an NVIDIA Jetson Nano.
• Implemented ORB-SLAM2 VSLAM with a stereo camera and integrated it into a Nanosaur robot using ROS2.
• Enabled remote Wi-Fi control and a server-based dashboard showing gas levels and a 3D map of the environment.

Fault-Tolerant Core using FXA Architecture

• Modeled REMO, a fault-tolerant core in gem5 using an in-order verifier per instruction.
• Extended the flow to model the FXA architecture alongside REMO fault tolerance.
• Evaluated performance impact using the SPEC CPU2006 benchmark suite.

Image Deblurring using Image Deconvolution

• Used a deep CNN to restore blurred images and reverse motion blur.
• Applied transfer learning on 12,240 image patches to reduce noise and artifacts and speed convergence.
• Achieved up to 92% deblurring accuracy with a TensorFlow model in Python.

• Undergraduate Research Award at IIT Bombay for research on the Secure Last-Level Cache
• Best Project Award for the Hazardous Gas Detection bot with VSLAM

• KVPY (Young Scientist Incentive Plan) fellowship, All-India Rank 191 out of ~50,000 in the SA stream, organized by IISc Bangalore
• Certificate of Merit in NSEA and NSEJS (top 1% of 53,900+ candidates), organized by IAPT (2018, 2019)