Out-of-Order Superscalar Processor
A 2-wide superscalar out-of-order processor designed and simulated in VHDL.
Advisor: Prof. Virendra Singh, IIT Bombay · Sep 2022 – Jan 2023
Led a four-member team to design a 2-wide superscalar out-of-order processor.
- Designed the logic for a 2-bit branch predictor, Fetch, Decode, Reservation Station, and ROB with register renaming.
- Implemented and tested the complete design in VHDL on Quartus Prime.