Fault-Tolerant Core using FXA Architecture
A fault-tolerant core modeled in gem5 using an in-order verifier per instruction.
Advisor: Prof. Virendra Singh, IIT Bombay · Aug 2023 – Dec 2023
Modeled REMO, a fault-tolerant core, in gem5 using an in-order verifier for each instruction.
- Extended the existing flow to model the FXA architecture alongside REMO fault tolerance.
- Evaluated the performance impact using the SPEC CPU2006 benchmark suite.